This invention relates to systems and methods of fabricating an embedded ferroelectric memory cell.
Today, in the semiconductor device fabrication industry and electronics industry several trends ore driving the development of new material technologies. First, devices (e.g. portable personal devices) are continuously getting smaller and requiring less power. Second, in addition to being smaller and more portable, these devices require more computational power and on-chip memory. In light of these trends, there is a need in the industry to provide a computational device that has a relatively large memory capacity and transistor functionality integrated onto the semiconductor chip. Preferably, this computational device will include a non-volatile memory so that if the battery dies, the contents of the memory will be retained. Examples of conventional non-volatile memories include electrically erasable, programmable read only memories (xe2x80x9cEEPROMxe2x80x9d) and flash EEPROMs.
A ferroelectric memory (FeRAM) is a non-volatile memory that utilizes a ferroelectric material as a capacitor dielectric that is situated between a bottom electrode and a top electrode. Ferroelectric materials, such as SrBi2Ta2O9 (SBT) and Pb(Zr,Ti)O3 (PZT), are being used in the fabrication of a wide variety of memory elements, including ferroelectric random access memory (FeRAM) devices. In general, ferroelectric memory elements are non-volatile because of the bistable polarization state of the ferroelectric material. In addition, ferroelectric memory elements may be programmed with relatively low voltages (e.g., less than 5 volts), and are characterized by relatively fast access times (e.g., less than 40 nanoseconds) and operational robustness over a large number of read and write cycles. These memory elements also consume relatively low power, may be densely packed, and exhibit radiation hardness.
Recent efforts to develop fabrication processes for ferroelectric materials have focused on the integration of FeRAM technology with semiconductor integrated circuit technology. Accordingly, such efforts have focused on scaling FeRAM capacitor areas, cell sizes and operating voltages downward in accordance with the scale of current integrated circuit dimensions. In addition to small lateral dimensions (i.e., dimensions parallel to the film surface), the ferroelectric dielectric must be relatively thin and must have a relatively low coercive field to achieve FeRAM devices having low operating voltages.
In addition to compatible device dimensions and operating characteristics, ferroelectric device fabrication processes should be compatible with standard semiconductor integrated circuit fabrication processes in order to achieve full integration of the two different technologies. As a result, substantial production efficiencies may be achieved by integration of the relatively new ferroelectric device technologies with the more mature and standardized integrated circuit fabrication processes.
The invention features integrated circuit structures comprising a transistor level, a ferroelectric device level, a first metal level, an inter-level dielectric level and a second metal level. The transistor level includes one or more semiconductor devices disposed over a substrate and an overlying transistor isolation layer having one or more contact vias extending therethrough. The ferroelectric device level includes one or more ferroelectric capacitors and a ferroelectric isolation layer having one or more vias extending therethrough.
The invention also features methods of forming the above-described integrated circuit structures.
In a first aspect of the invention, the ferroelectric device level is disposed over the transistor isolation layer and the ferroelectric isolation layer has one or more vias that are laterally sized larger than corresponding contact vias extending through the transistor isolation layer and aligned therewith.
In a second aspect of the invention, the first metal level and the ferroelectric device level are integrated into the same level. In some embodiments in accordance with this aspect, the integrated first metal and ferroelectric device level has a thickness corresponding substantially to the ferroelectric capacitor heights. In other embodiments, the integrated first metal and ferroelectric device level may be substantially non-planar with a reduced thickness in non-capacitor regions.
In a third aspect of the invention, the ferroelectric device level is disposed over the first metal level.
In a fourth aspect of the invention, the ferroelectric device level is disposed over an inter-level dielectric level that, in turn, is disposed over the first metal level.
In a fifth aspect of the invention, the ferroelectric device level is disposed over the transistor isolation layer and the ferroelectric isolation layer has one or more vias extending through the ferroelectric isolation layer and the transistor isolation layer.
Embodiments of the invention may include one or more of the following features.
The contact vias preferably are filled with tungsten contact plugs. The ferroelectric capacitors preferably are formed over respective tungsten contact plugs.
In some embodiments, top and bottom surfaces of each of the levels are substantially planar.
Some integrated circuit structure embodiments may include other metal levels in addition to the first and second metal levels mentioned above.
Other features and advantages of the invention will become apparent from the following description, including the drawings and the claims.